Counter ramp converter

When the digital to analog converter output voltage is greater than the input voltage the state of the comparator becomes low. No pulse will be applied to the counter. Instead, the low output of the comparator goes to the control circuit which in return latches the output of the counter and the counter gets reset.

So, we conclude that the latched output is directly proportional to the input voltage. This is the whole procedure and after completion, again the input voltage is sampled and new conversion initiates. The counter resets for every new conversion i. The analog to digital conversion time is dependent on the magnitude of the input voltage. The greater the applied voltage the more time the analog to digital converter takes for the analog data conversion. The following figure shows the typical conversion pattern of the counter type analog to digital converter:.

It is clearly visible that the output of the counter type digital to analog converter increases until it reaches the input voltage. As it crosses the magnitude of the input voltage, the counter resets and the next conversion begins.

The green bar determines the time taken by the analog to digital converter for one conversion. We can also see that the part where the input voltage is increased, the conversion time has also increased. It is the time taken by the analog to digital converter to completely transform the analog input to digital output. Where N is the number of bits of analog to digital converter and Tclk is the duration of the clock pulse.

The input voltage becomes equal to the full-scale output voltage of the DAC if all the input bits are 1. This conversion time equation shows its dependency on the resolution and clock frequency. If the bits of digital to analog converter increases, the resolution of the counter type ADC increases which ultimately increases the conversion time.

So there is a trade-off between the resolution and conversion time. An increase in clock frequency can reduce the conversion time but it is also limited by the response time of the components of the analog to digital converter.

Enter your email address to subscribe to this blog and receive notifications of new posts by email. Email Address. Notify me of follow-up comments by email. As long as the analog and ramp generator inputs to the comparator differ in magnitude, the clock pulse generator will be permitted to transmit pulses at a constant repetition rate through the gate into the counter. When the two inputs to the comparator become equal as a result of the linearly rising sawtooth the comparator will generate a stop signal which disables the gate circuit and ends the comparison time interval.

The disabled gate circuit blocks the flow of pulses from the clock pulse generator to the counter. The number of pulses accumulated in the counter during the comparison time interval is proportional to the amplitude of the analog input voltage.

The counter indication is the desired digital representation of the input signal. All Rights Reserved.